1. Field of the Invention
The present invention relates to a display device and a shift register array for driving a pixel array, and more specifically, to a display device and a shift register array for replacing a malfunctioned shift register.
2. Descriptions of the Related Art
In recent years, the development of flat panel displays progresses more and more rapidly as having gradually taken the place of traditional cathode ray tube displays. Current flat panel displays include organic light-emitting displays (OLEDs), plasma display panels (PDPs), liquid crystal displays (LCDs) and field emission displays (FEDs). No matter what type it is, a shift register array thereof has to supply a driving signal for scan lines of the pixel array to function the flat panel display normally.
FIG. 1 is a schematic diagram illustrating a flat panel display of the prior art. The flat panel display 1 comprises a pixel array 11, a peripheral circuit 13, and a shift register array 15. The pixel array 11 comprises a plurality of scan lines (only shown as 111, 112, . . . , 116 for the sake of simplification) and data lines (only shown as 131, 132, . . . , 136 for the sake of simplification). The shift register array 15 comprises a plurality of shift registers (only shown as 151, 152, . . . , 156 for the sake of simplification), wherein each shift register drives a scan line. The peripheral circuit 13 drives the data lines 131, 132, . . . , 136. The shift registers 151, 152, . . . , 156, connected together in series, comprise thin-film transistors 1511, 1521, . . . , 1561, respectively. Except the first stage shift register 151 which is activated by an activation signal 10 that is directly received by a signal input terminal 1513 of the same, signal input terminals 1523, 1533, 1543, 1553, 1563 of other stage shift registers 152, . . . , 156 respectively receive driving signals outputted from signal output terminals 1515, 1525, 1535, 1545, 1555 of the previous stage shift registers as the activation signals. The signal output terminals 1515, 1525, 1535, 1545, 1555, 1565 are also connected to the scan lines 111, 112, . . . , 116 respectively to drive the scan lines. The shift registers 151, 152, . . . , 156 further receive a positive clock CK, a negative clock XCK, and a DC power source VSS to function. The received clocks of the thin-film transistors of the adjacent shift registers must be opposite. For example, the thin-film transistors 1511, 1531, 1551 of the odd stage shift registers 151, 153, 155 receive the positive clock CK, and the thin-film transistors 1521, 1541, 1561 of the even stage shift registers 152, 154, 156 receive the negative clock XCK. Therefore, the activation signal 10 can be passed down stage by stage, and the scan lines 112, 112, . . . , 116 can be driven sequentially.
If one of the shift registers malfunctions during the manufacturing process shown as the shift register 153 in FIG. 1, the corresponding scan line 113 can not be driven. Moreover, the operations of the following shift registers are also influenced since they are connected in series. When the panel size is large or the resolution is high, the influence of the above-mentioned situation will be more serious. Therefore, it is an objective in improving the production yield of manufacturing the flat panel displays and providing a backup solution to making up the malfunction.